Code latency (msec)
4 layer stack
10 layer
14
19
37
32
81
Total
4
10
8
14
Up Stack
6
+ 2
7
8
7
20
Up Transport
6
6
8
27
Down
Transport
2
+ 4
2
13
9
20
Down Stack
HAND
MACH
ORIG
MACH
ORIG
(See
paper for CPU cycles and TLB misses)
